The present application relates generally to the electrical, electronic and computer arts and, more particularly, to metal interconnect structures and their fabrication.
With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
Silicon-based devices typically include multiple interconnect metallization layers above a device (front-end-of-line/FEOL) layer that contains field-effect transistors (FETs), memory devices, or other structures. Middle-of-line (MOL) processing includes steps typically used for fabricating metal contacts for logic circuitry components such as field-effect transistors (FETs), resistors, diodes, and capacitors. Back-end-of-line (BEOL) processing involves the creation of metal interconnecting wires that connect the devices formed in FEOL processing to form electrical circuits. The interconnecting wires are electrically isolated by dielectric layers. BEOL process technologies may employ copper to form BEOL interconnects. Copper interconnects are characterized by relatively low electrical resistance in the BEOL interconnect structures, resulting in improved conduction and higher performance. Defects in copper interconnect structures such as voids, recesses and/or under-fill can result in loss of line yield, circuit failures, and wafer scrap. Attempts to address such defects have included the stripping of all layers, including interconnect metal and dielectric layers, and redepositing and patterning the same. Patterning steps can become challenging at advanced nodes.
To mitigate electromigration in BEOL copper interconnect structures, a capping layer is typically formed over the BEOL copper wiring. The capping layer is formed with a material that serves to inhibit diffusion, oxidation, and/or electromigration from the top surface of the copper interconnect structures and/or to prevent oxidation of the copper interconnect structures.
A BEOL structure typically includes a dielectric layer and a metal interconnect structure embedded in the dielectric layer. The dielectric layer, which may include multiple layers, may be referred to as an inter-layer dielectric layer or ILD layer. Trench openings are conventionally formed in the ILD layer by using, for example, known damascene techniques. Photolithography and etching steps follow ILD layer deposition. Specifically, a photoresist is applied over the ILD layer. The photoresist can be applied by any suitable technique, including, but not limited to coating or spin-on techniques. A mask (not shown), which is patterned with shapes defining trench openings (and possibly contact holes) to be formed, is provided over the photoresist, and the mask pattern is transferred to the photoresist using a photolithographic process, which creates recesses in the uncovered regions of the photoresist. The patterned photoresist is subsequently used to create the same pattern of recesses in the ILD dielectric layer through conventional etching typically used for forming trenches and contact holes. A dry etch (for example, a reactive ion etch) may be employed to form such trenches and contact holes. The etching selectively removes a portion of the ILD layer. The depth(s) of the trench openings can be controlled by using a timed etching process. Alternatively, the dielectric layer may include multiple layers that may be selectively etched. In such a case, the etch process selectively removes the upper layer(s) of the ILD layer, stopping at a lower layer thereof that forms an etch stop. After formation of the trench openings, the photoresist may be stripped by ashing or other suitable process from the ILD layer.
A further stage in the fabrication process includes depositing a conformal layer of liner material. The conformal layer of liner material lines the sidewall and bottom surfaces of the trenches or other openings within the ILD layer. The liner material may include one or more thin layers of material such as, for example, tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), cobalt (Co), tungsten (W), tungsten nitride (WN), titanium-tungsten (TiW), tungsten nitride (WN) manganese (Mn), manganese nitride (MnN) or other liner materials (or combinations of liner materials) such as RuTaN, Ta/TaN, CoWP, NiMoP, NiMoB) which are suitable for the given application. The thin liner serves as a barrier diffusion layer and adhesion layer. The conformal layer of liner material is deposited using known techniques such as CVD, ALD, or PVD. A thin conformal Cu seed layer can be deposited over the surface of the liner using PVD, followed by the electroplating of Cu to fill the damascene (or dual damascene) openings in the ILD layer. A thermal anneal stage follows electroplating.
The overburden liner, seed, and metallization materials are then removed by performing a three step chemical mechanical polishing process (CMP) to planarize the surface of the semiconductor structure down to the ILD layer. A metal cap layer is selectively deposited on the exposed metal interconnect layer within the trenches. For example, metals such as cobalt, ruthenium or manganese may be deposited using chemical vapor deposition or atomic layer deposition to form the cap layers. Post-deposition cleaning may be required to ensure there is no leakage or degradation resulting from possible metal residues on the resulting structure. Cleaning and/or other steps that may be performed subsequent to capping.